Publications
Filters: First Letter Of Title is A [Clear All Filters]
"Automatic Generation of Efficient Accelerators for Reconfigurable Hardware",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Abstract
Download: paper (2.77 MB)
ARQ: A Multi-Class Admission Control Protocol for Heterogeneous Datacenters,
, Stanford, Stanford University, 01/2013.
Download: tech report (663.54 KB)
"Accurate Modeling and Generation of Storage I/O for Datacenter Workloads",
Exascale Evaluation and Research Techniques Workshop (EXERT), in conjunction with ASPLOS, Newport Beach, CA, 03/2011.
Download: paper (715.38 KB); slides (2.09 MB)
"An Analysis of Interconnection Networks for Large Scale Chip-Multiprocessors",
ACM Transactions on Architecture and Code Optimization (TACO), vol. 7, no. 1, 04/2010.
Download: paper (1.7 MB)
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)