| Week | Date | Topic | Readings | Problem Sets | Labs | Other Handouts |
| 1 | 1/07 | No class today, first class is on Wednesday, January 9th. | ||||
| 1/09 | Overview. Digital abstraction. Boolean algebra. Combinational logic. Verilog introduction. (pdf) | 1, 3, 6.1-6.4 | Problem Set 1 Out (pdf) | Lab 0: Intro to Lab Lab 0: UCF File |
• Course Reader Chapters 1-12 • Course Policy • Lab/Section Signup Sheet |
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| 1/11 | Section 1 | |||||
| 2 | 1/14 | Combinational logic. Karnaugh maps. Covering hazards. Writing good Verilog. | 6.5-6.11, 7 | Problem Set 2 Out | Lab 1: Tic-tac-toe Lab 1: Starter Files |
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| 1/16 | Combinational building blocks: mux, decode, encoder, comparator. Verilog examples. | 8, 9 | Problem Set 1 Due | |||
| 1/18 | Section 2 | Lab 2: Mu-Law FP Adder Lab 2: Starter Files |
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| 3 | 1/21 | Martin Luther King Day. No class. | ||||
| 1/23 | Number representation. Negative numbers. Two's complement. Arithmetic units: adders and multipliers. | 10, 11 | Problem Set 2 Due | |||
| 1/25 | Section 3 | |||||
| 4 | 1/28 | Combinational review. | Lab 3: Bicycle Light FSM Lab 3: Starter Files |
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| 1/30 | Quiz 1 | |||||
| 2/1 | Section 4 | |||||
| 5 | 2/4 | Sequential logic. Design: flip-flops, FSMs. State assignment and one hot. Traffic controller example. | 14 | Problem Set 3 Out | Lab 4: Music Synthesizer Lab 4: Sine waves explanation Lab 4: Quarter sine wave ROM graph Lab 4: Starter Files |
• Course Reader Chapters 14-16 |
| 2/6 | Datapath building blocks: counters, timers, and shift registers. Datapath/control partitioning. | 16 | ||||
| 2/8 | Section 5 | |||||
| 6 | 2/11 | Microcode. Traffic light controller example. | 18 | Problem Set 4 Out | Lab 5: Music Synthesizer with Wave Displays Lab 5: Starter Files |
• Course Reader Chapters 17 and 18 |
| 2/13 | System partitioning: data path and control, resource sharing, buses and arbitration. | 20, 21 | Problem Set 3 Due | • Course Reader Chapters 19-21 | ||
| 2/15 | Section 6 | Final Project Spec Final Project Resources |
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| 7 | 2/18 | President's day. No class. | ||||
| 2/20 | Concurrency, pipelines, client/server, and work farms. Token model. Timing. FIFOs, clock domains. Examples. | Problem Set 5 Out | ||||
| 2/22 | Section 7 | Problem Set 4 Due | ||||
| 8 | 2/25 | Timing analysis. Setup and hold times. | 15 | Problem Set 6 Out | Project Checkpoint 1 due | • Course Reader Chapters 22-25 |
| 2/27 | Metastability and synchronization failure. Common synchronizer errors. Gray codes, revisited. | 24, 25 | Problem Set 5 Due | |||
| 2/29 | Section 8 | |||||
| 9 | 3/3 | Sequential Review | Problem Set 6 Due | |||
| 3/5 | Quiz 2 | |||||
| 3/7 | ||||||
| 10 | 3/10 | Course Review. | Project Checkpoint 2 due | |||
| 3/12 | No lecture. | |||||
| 3/14 | ||||||
| 11 | 3/17 | Exam period | ||||
| 3/19 | Exam period | |||||
| 3/21 | Exam period | Project Due (tentative) | ||||
| 12 | 3/24 | |||||
| 3/26 | ||||||
| 3/28 |