Effect of Switch Selection on Efficiency

I was curious how inverter transistor losses would effect the efficiency of the device, because of the extra performance demands placed on the inverter by the low power factor of the phases. The switches need to provide both relatively high currents and block high voltages for a given power output. This both dramatically increases costs and reduces efficiency.

​To look at these effects created a simple power loss model for two potential transistors: a very high cost, high voltage blocking, low on resistance SiC MOSFET, and a much lower cost IGBT.

CREE C2M0040120D SiC MOSFET

  • ~$30.00 each
    • 60 Switches (15 full bridges) -> Inverter Cost ~$1800 YIKES!!!!
  • Rds(on) = 40 mΩ 
  • Switching Energy (~0.2mJ/Cycle @ ~10A)
  • 200V Blocking
  • Loss Model:
    • Max V/kRPM/Turn = 1.5 -> Max V/Turn @ 60kRPM = 90V
    • N turns = 13
    • Frequency = 10kHz
    • Ploss/Phase = 0.2mJ*10000Hz + 40 mΩ*(Iphase/13)2 
  • Ploss/Phase = 2+0.04*(Iphase/13)2 

​Infineon IPG440N65H5

  • ~$1.60 each
    • Inverter Cost ~$100 <- Still expensive, but much more reasonable
  • Switching Energy = ~0.6mJ
  • 650V Blocking
  • Loss Model:
  • 90V/Turn -> N turns = 7
  • Conduction loss -> Red line
    • Vdrop = 1.2 + 0.0143*I
  •  Ploss/Phase = ​ 6+0.0143*(Iphase/7)2 +1.2*Iphase/7 

"Re-optimization"

For the optimization, I simply swept through the possible pole-arc angles. The advantage of this, over say some gradient descent, is that now I can use the data to find new optimum points for different objective function. So, I included the above loss models back in to the efficiency computation, and found the optimum designs for both transistor choices. This time, I was looking for the global optimum across all corner radii, because it did not have the power factor benefits I had hoped for. It turns out for all cases, the 42 deg pole arc, 0mm radius was optimal. This is because that design has the highest torque per current, so conduction losses are penalized the least for that motor. It was also the optimal design from a purely electromechanical sense as well.
E+M losses only: 
Mean Efficiency : 98.3%
Round Trip: 96.6%
With SiC FET Losses
Mean Efficiency : 96.6%
​Round Trip: 93.4%
With IGBT Losses
Mean Efficiency : 94.4%
​Round Trip: 89.2%
Clearly the transistor losses are significant in both cases. With the SiC MOSFETs, the losses are roughly evenly divided between the motor and inverter. This is actually not that bad, and the round trip efficiency is still acceptable. However such an inverter would be prohibitively expensive, rendering any cost-advantage of the reluctance motor useless. The IGBT inverter loss is over twice that of the SiC FET inverter loss, and has a significant effect on the mean round trip efficiency. While the IGBT inverter is more reasonable in terms of cost, it is still on the expensive side. Thus, further work is necessary to bring the phase power factor up to make the design feasible from an inverter design perspective.