H.-S. Philip Wong

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Professor of Electrical Engineering

Willard R. and Inez Kerr Bell Professor in the School of Engineering

 

Education:

B.Sc. Hons. (1982) University of Hong Kong, M.S. (1983) State University of New York, Stony Brook, and Ph.D. (1988) Lehigh University. 

 

Biography:

H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering. He joined Stanford University as Professor of Electrical Engineering in September, 2004.

 

From 1988 to 2004, he was with the IBM T.J. Watson Research Center where he did many of the early research works that have led to product technologies.

 

From 2018 to 2020, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world. Since 2020, he has been the Chief Scientist of TSMC.

 

Professor Wong’s research aims to translate discoveries in science into practical technologies. His works have contributed to advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging. His present research covers a broad range of topics including carbon electronics, 2D layered materials, wireless implantable biosensors, directed self-assembly, device modeling, brain-inspired computing, non-volatile memory, and 3D system integration.

 

He is a Fellow of the IEEE and received the IEEE Electron Devices Society J.J. Ebers Award, the Society’s highest honor to recognize outstanding technical contributions to the field of electron devices that have made a lasting impact.

 

He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and has been the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits since 2014.

 

He has held leadership positions at major multi-university research centers of the National Science Foundation and the Semiconductor Research Corporation. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.

 

 

RESEARCH GROUP: Nanoelectronics and Nanotechnology

List of current and former students, model and research data downloads, and news are here: http://nano.stanford.edu

 

Recent talks on video:

DARPA ERI Summit 2020: https://youtu.be/cJh7EMWa6J0

DAC 2020: https://youtu.be/zexC_As261s

HotChips 2019: https://youtu.be/O5UQ5OGOsnM

MIT MTL Seminar 2018: https://www.mtl.mit.edu/seminars/future-transistor-integration

 

Education video on nanotechnology:

NSF Science Nation video on carbon nanotube nanosystems (produced by the National Science Foundation)

Carbon nanotube technology (funded by the National Science Foundation)

CNT at Stanford: Long, medium, short (funded by the National Science Foundation)

 

Some time ago, someone posed this question to me: “What comes after the computer chip?” Having spent most of my career on advancing semiconductor technology, which is the physical foundation of the computer chip, I find this question worth thinking about. So I wrote this blog on Slate.

 

In 2017, I was interviewed by the National Nanotechnology Coordination Office (NNCO) of the White House. I talked about our research in this podcast on nano.gov.

 

RESEARCH AREAS: Nanotechnology, nanoelectronics, semiconductor technology, solid-state devices, Si CMOS, solid-state imaging.

 

21st century information technology (IT) must process, understand, classify, and organize vast amount of data in real-time. 21st century applications will be dominated by data-centric computing operating on Tbytes of active data with little data locality. At the same time, massively redundant sensor arrays sampling the world around us will give humans the perception of additional “senses” blurring the boundary between biological, physical, and cyber worlds. Abundant-data processing, which comprises real-time big-data analytics and the processing of perceptual data in wearable devices, clearly demands computation efficiencies well beyond what can be achieved through business as usual.

 

The key elements of a scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing performance (energy-execution time product) for future computing workloads are: massive on-chip memory co-located with highly energy-efficient computation, enabled by monolithic 3D integration using ultra-dense and fine-grained massive connectivity. There will be multiple layers of analog and digital memories interleaved with computing logic, sensors, and application-specific devices.  We call this technology platform N3XT – Nanoengineered Computing Systems Technology. N3XT will support computing architectures that embrace sparsity, stochasticity, and device variability.

 

[N3XT: Nano-engineered Computing Systems Technology. Monolithic 3D integration of memory immersed in logic, connected by ultra-dense vertical connections.]

 

Logic:

For transistors it is important to have an atomically thin channel that enables gate length scaling while maintaining good carrier transport required for a high current drive. At the same time, parasitic resistance from the contacts and parasitic capacitance from the device structure must be minimized. Currently, we are working on the use of carbon nanotube (CNT) and two-dimensional layered materials (the transition metal dichalcogenide family of materials) as the atomically thin channel. We are also developing techniques to minimize the contact resistance and the parasitic capacitance. By building practical nanosystems of these emerging technologies, we learn how to solve fundamental device and materials science problems that have system-level impact.

 

[Aligned carbon nanotube growth (Albert Lin, Nishant Patil, Hong-Yu (Henry) Chen, Luckshitha Liyanage)]

 

[10-nm contact to carbon nanotube (Greg Pitner)]

 

[A microprocessor made entirely out of carbon nanotubes with > 10,000 CNTs and > 2 billion carbon atoms (Max Shulaker et al.)]

 

 

Memory:

I started doing research on memory devices around 2003. Research on memory had been rather “predictable” for many years until recently. It was predictable because the major advances for memory devices involved scaling down the physical dimensions of essentially the same device structure using basically the same materials. The situation has changed in the last two decades. Memory devices are beginning to be difficult to scale down. But perhaps the most important change is that new applications and products (e.g. mobile phones, tablets, enterprise-scale disk storage) in the last decade are often enabled by advances in memory technology, in particular solid-state non-volatile memories.

 

Our research on memory devices broadly covers phase change memory (PCM), metal oxide resistive switching memory (RRAM), ferroelectric memory and related topics such as selectors. We aim to understand the fundamental physics of these devices and develop models of how they work. We explore the use of various materials and device structures (e.g. 3D vertical RRAM) to achieve desired characteristics. We are working on building memory systems that are monolithically integrated in 3D with logic computing elements.

 

Picture4Picture7

[Resistive switching Random Access Memory (RRAM) array (Joon Sohn)]

 

 

[3D Resistive Switching Random Access Memory (3D RRAM) (Zizhen (Jane) Jiang, Shengjun (Sophia) Qin, Hong-Yu (Henry) Chen, Shimeng Yu, and collaborators at Peking University.)]

 

Picture6

[3D RRAM made with atomically thin (0.3 nm) plane electrode (Joon Sohn, Seunghyun Lee et al.)]

 

[Nanoscale metal oxide RRAM fabricated by self-assembly patterning (Yi (Alice) Wu, He (Linda) Yi et al.)]

 

 

Compute-in-Memory:

We are developing novel memory devices and circuits that implement neural network accelerators on a logic platform that has high-density on-chip non-volatile memories.

 

[Compute-in-memory chip with data flow re-configurability, W. Wan and UCSD, Tsinghua U, Notre Dame U. collaborators]

 

[Demo of image recovery using RRAM compute-in-memory chip (@ISSCC 2020 and @SympVLSI 2020) https://youtu.be/b7ITxmfaLBk]

 

For examples of our works, see

 

1.     W. Wan, R. Kubendran, B. Gao, S. Joshi, P. Raina, H. Wu, G. Cauwenberghs, H.-S. P. Wong, “A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping  For Energy-Efficient RRAM-Based In-Memory Computing,” Symp. VLSI Technology, Honolulu, HI, paper TM2.2, June 15 – 19, 2020.

2.     W. Wan, R. Kubendran, S.B. Eryilmaz, W. Zhang, Y. Liao, D. Wu, S. Deiss, B. Gao, P. Raina, S. Joshi, H. Wu, G. Cauwenberghs, H.-S. P. Wong, “A 74 TOPS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models,” International Solid State Circuits Conference (ISSCC), paper 33.1, pp. 498 – 499, San Francisco, CA, February 18 – 20, 2020.

3.     H. Li, M Bhargav, P. N. Whatmough, H.-S. P. Wong, “On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators,” 56th ACM/IEEE Design Automation Conference (DAC), pp 1 – 6, 2019.

4.     H. Li, T.F. Wu, A. Rahimi. K.-S. Li, M. Rusch, C.-H. Lin, J.-L. Hsu, M.M. Sabry, S.B. Eryilmaz. J. Sohn, W.-C. Chiu, M.-C. Chen, T.-T. Wu, J.-M. Shieh, W.-K. Yeh, J. M. Rabaey, S. Mitra, and H.-S. P. Wong, “Hyperdimensional Computing with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language Recognition,” IEEE International Electron Devices Meeting (IEDM), paper 16.1, December 5 – 7, San Francisco, 2016

 

Picture8 

[Hyperdimensional computing using 3D RRAM (Haitong Li and collaborators at UC Berkeley and National Nano Device Laboratory, Taiwan)]

 

 

CellChips – Electronically programmable synthetic biology:

In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring.  We are developing techniques to place micron-sized sensor chip inside each cell.

 

These CellChips will be equipped with molecular sensors and effectors that allow them to sense and trigger different cellular signaling or gene regulatory pathways. Using bi-directional radio communication with the sensor and effector functions, we will be able to change connections between cellular signaling pathways at will, in real time, without the need to generate new genetic constructs. This technology will provide to synthetic biology the same rapid prototyping and reconfigurability that was brought to electronics by field-programmable gate array (FPGA) technology deployed in data centers, and a variety of information and communication technologies that require reconfiguration post-deployment.

 

This may also open up an array of new biomedical applications that range from novel medical diagnostic and therapeutic tools that operate at single cell level to a novel class of autonomously operating intrabody nanobiosensors.

Nanofabrication and integrated electronics are the key enabling technologies of this research.

 

Picture3 

[Uptake of RFID by living cells (Xiaolin (Jasmine) Hu, Mimi Yang, Kokab Parizi)]

 

 

Examples of our research can be found in the publications and conference presentations listed below.

 

PUBLICATIONS: https://scholar.google.com/citations?user=HWxGEesAAAAJ&hl=en

 

Recent and Upcoming Invited Presentations:

 

1.      H.-S. P. Wong, “Technology for 3D ICs,” invited plenary paper, International Interconnect Technology Conference (IITC), San Jose, CA, October 5 – 9, 2020.

2.      H.-S. P. Wong, “A New Metric for Gauging Progress of Semiconductor Technology,” invited plenary paper, International Conference on Solid State Devices and Materials (SSDM), Toyama Prefecture, Japan, September 27 – 30, 2020.

3.      H.-S. P. Wong, “The Future is System Integration,” invited keynote, DARPA ERI Summit (ERI Summit), Seattle, WA, August 18 – 20, 2020.

4.      H.-S. P. Wong, “Technology from 3D ICs to 3D System-on-a-Chip,” invited plenary paper, Design Automation Conference (DAC), San Francisco, July 20 – 22, 2020.

5.      H.-S. P. Wong, “IC Technology – What Will the Next Node Offer Us?” invited plenary paper, Hot Chips: A Symposium on High Performance Chips, Stanford, CA, August 18 – 20, 2019

6.      H.-S. P. Wong, “Progress towards a carbon nanotube transistor logic technology,” invited plenary paper, NT19: International Conference on the Science and Application of Nanotubes and Low-Dimensional Materials, Wurzburg, Germany, July 21 – 26, 2019.

7.      H.-S. P. Wong, “Reaching for the N3XT 1,000× of Computing Energy Efficiency,” invited plenary paper, Device Research Conference (DRC), Santa Barbara, CA, June 24 – 27, 2018.

8.      H.-S. P. Wong, “On to the Next Fifty Years – Guideposts from the Past Fifty Years,” invited plenary paper, Semiconductor Integrated Circuit Technology Workshop (SICTW) at West Lake, Zhejiang University, Hangzhou, China, November 6 – 9, 2017.

 

Selected Recent and Upcoming Conference Publications:

 

1.      G. Pitner, Z. Zhang, Q. Lin, S.-K Su C. Gilardi, C. Kuo, H. Kashyap, T. Weiss, Z. Yu, T.-A. Chao, L.-J. Li, S. Mitra, H.-S. P. Wong, J. Cai, A. Kummel, P. Bandaru, M. Passlack, “Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length,” International Electron Devices Meeting (IEDM), paper 3.5, December 14 – 16, San Francisco, 2020.

2.      W. Wan, R. Kubendran, B. Gao, S. Joshi, P. Raina, H. Wu, G. Cauwenberghs, H.-S. P. Wong, “A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping  For Energy-Efficient RRAM-Based In-Memory Computing,” Symp. VLSI Technology, Honolulu, HI, paper TM2.2, June 15 – 19, 2020.

3.      W. Wan, R. Kubendran, S.B. Eryilmaz, W. Zhang, Y. Liao, D. Wu, S. Deiss, B. Gao, P. Raina, S. Joshi, H. Wu, G. Cauwenberghs, H.-S. P. Wong, “A 74 TOPS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models,” International Solid State Circuits Conference (ISSCC), paper 33.1, pp. 498 – 499, San Francisco, CA, February 18 – 20, 2020.

4.      H. L. Chiang, T. C. Chen, J. F. Wang, S. Mukhopadhyay, W. K. Lee, C. L. Chen, W. S. Khwa, B. Pulicherla, P. J. Liao, K. W. Su, K. F. Yu, T. Wang, C. H. Diaz, H.-S. P. Wong, J. Cai, “Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs,” Symp. VLSI Technology, Honolulu, HI, paper TC1.3, June 15 – 19, 2020.

5.      Ang-Sheng Chou, Pin-Chun Shen, Chao-Ching Cheng, Li-Syuan Lu Wei-Chen Chueh, Ming-Yang Li, Gregory Pitner, Wen-Hao Chang, Chih-I Wu, Jing Kong, Lain-Jong Li, and H.-S. P. Wong, “High On-Current 2D nFET of 390 µA/µm at VDS = 1V using Monolayer CVD MoS2 without Intentional Doping,” Symp. VLSI Technology, Honolulu, HI, paper TN1.7, June 15 – 19, 2020.

6.      E.R. Hsieh, M. Giordano, B. Hodson, A. Levy, S.K. Osekowsky, R.M. Radway, Y.C. Shih, W. Wan, T. F. Wu, X. Zheng, M. Nelson, B.Q. Le, H.-S.P. Wong, S. Mitra, and S. Wong, “High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning,” International Electron Devices Meeting (IEDM), December 9 – 11, San Francisco, 2019.

7.      H. Li, M Bhargav, P. N. Whatmough, H.-S. P. Wong, “On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators,” 56th ACM/IEEE Design Automation Conference (DAC), pp 1 – 6, 2019.

8.     C.-H. Wang, C. McClellan, Y. Shi, X. Zheng, V. Chen, M. Lanza, E. Pop, and H.-S. P. Wong, “3D Monolithic Stacked 1T1R cells using Monolayer MoS2 FET and hBN RRAM Fabricated at Low (150°C) Temperature,” International Electron Devices Meeting (IEDM), paper 22.5, December 1 – 5, San Francisco, 2018.     

 

Recent Invited Journal Articles:

 

1.      D. Akinwande, C. Huyghebaert, C.-H. Wang, M. I. Serna, S. Goossens, L.-J. Li, H-S. P. Wong, and F. H. L Koppens. "Graphene and two-dimensional materials for silicon technology," Nature 573, no. 7775 (2019): 507-518.

2.      M. D. Bishop, H.-S. P. Wong, S. Mitra, and M. Shulaker, “Monolithic 3-D Integration,” invited review article, IEEE Micro, Nov/Dec, 2019.

3.      M. M. S. Aly, T.F. Wu, A. Bartolo, Y. H. Malviya, W. Hwang, G. Hills, I. Markov, M. Wooters, M.M. Shulaker, H.-S. P. Wong, S. Mitra, “The N3XT Approach to Energy-Efficient Abundant-Data Computing,” invited paper, Proceedings of the IEEE, vol. 107, pp. 19 – 48 (2019).

4.      D. Ielmini and H.-S. P. Wong, “In-memory Computing with Resistive Switching Devices,” Nature Electronics, invited review paper, vol. 1, pp. 333 – 343, June 2018.

5.      T.N. Theis and H.-S. P. Wong, “The End of Moore's Law: A New Beginning for Information Technology,”  invited paper, IEEE Computing in Science & Engineering, vol. 19, no. 2, pp. 41-50, Mar.-Apr. 2017.

 

Selected Recent Journal Articles:

 

1.      H. -S. P. Wong, K. Akarvardar, D. Antoniadis, J. Bokor, C. Hu, T.-J. King-Liu, S. Mitra, J.D. Plummer, S. Salahuddin, "A Density Metric for Semiconductor Technology," Proceedings of the IEEE, vol. 108, no. 4, pp. 478-482, April 2020.

2.      R. S. Park, H. J. K. Kim, G. Pitner, C. Neumann, S. Mitra, H.-S. P. Wong, “Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function,” J. Appl. Phys., vol. 128, no. 4, p. 045111 (2020).

3.      R. V. Zarcone, J.H. Engel, S.B. Eryilmaz, W. Wan, S. Kim, M. BrightSky, C. Lam, H.-L. Lung, B.A. Olshausen, and H.-S. P. Wong, “Analog Coding in Emerging Memory Systems,” Scientific Reports, 10, 6831 (2020).

4.      S. Qin, Z. Jiang, H. Li, S. Fujii, D. Lee, S. Wong, H.-S. P. Wong, “Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling,” IEEE Trans. Electron Devices, Vol 66, Issue 12, pp. 5139 – 5146, 2019.

5.      Z. Jiang, S. Qin, H. Li, S. Fujii, D. Lee, S. Wong, H.-S. P. Wong, “Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture,” IEEE Trans. Electron Devices, Vol 66, Issue 12, pp. 5147 – 5154, 2019.

6.      K. L. Okabe, A. Sood, E. Yalon, C. M. Neumann, M. Asheghi, E. Pop, K.E. Goodson, and H.-S. P. Wong, “Understanding the switching mechanism of interfacial phase change memory,” Journal of Applied Physics 125, 184501 (2019).

7.      L. Li, Z. Zhu, A. Yoon, H.-S. P. Wong, “In-Situ Grown Graphene Enabled Copper Interconnects With Improved Electromigration Reliability,” IEEE Electron Device Letters, Vol. 40, Issue 5, pp. 815 – 817, May, 2019.

 

Selected Publications Prior to Joining Stanford:

 

1.      T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.

2.      H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).

3.      J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, “Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).

4.      H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).

5.      J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.

6.      H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.

7.      H.-S. P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube Field Effect Transistors – Fabrication, Device Physics, and Circuit Implications”, IEEE International Solid State Circuits Conference (ISSCC), p. 370 – 371, 2003.

8.      H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.

9.      J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002

10.   L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes,  J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.

11.   B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.

12.   K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.

13.   R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.

14.   D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.

15.   H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.

 

 

Book:

H.-S. P. Wong and D. Akinwande, “Carbon Nanotube and Graphene Device Physics,” Cambridge University Press, 2011.  (ISBN-13: 9780521519052). Available at Amazon.com.

 

CNT book cover

 

 

CLASSES:

EE 21N Freshman Seminar (new class since Autumn, 2006, next offering: Winter 2018) – “What is Nanotechnology?” – not offered due to COVID-19 and lab component of the class).

EE 309A/B (new class since Autumn, 2020/Winter 2021 (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 271, EE 316, EE 313, EE 311 (with Prof. Priyanka Raina)

EE 316 (Winter) “Advanced VLSI Devices”

EE 320 (evolved from EE 218, new in 2008/09) “Nanoelectronics” (There is no required textbook for this course) – Prerequisite EE222, EE216 and knowledge of solid state physics,  Recommended: EE 223, 228, or 316.

             (slides for 1st lecture of EE 218 back in Autumn 2005) (rather old, kept here for historical reasons, as a time capsule)

EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)

 

EE 310 Seminar slides:

October 5, 2004. Download here. (rather old, kept here for historical reasons, as a time capsule)

 

Contacts: 

H.-S. Philip Wong

Department of Electrical Engineering and Stanford SystemX Alliance,

Paul G. Allen 312X

420 Via Palou,

Stanford University, Stanford, CA 94305-4075

Email: hspwong AT stanford DOT edu

Phone: +1-650-725-0982

 

Administrative Assistant: Fely Barrera

Email:  fbarrera AT Stanford DOT edu

Phone: +1-650-723-1349

 

Directions to campus office and parking information: https://nano.stanford.edu/contact-us

 

Last modified:

December 30, 2020