Ana and Heiner's work on ReFlex, which won the NVMW Memorable Paper Award, is summarized in ACM SIGARCH Computer Architecture Today.
News feed
-
ReFlex in ACM SIGARCH Computer Architecture Today [March 2018]
-
Memory Hierarchy for Web Search in the news [March 2018]
Our work with Google on improving the memory hierarchy for web search was discussed by The Next Platform in its article Google And Its Hyperscale Peers Add Power To The Server Fleet. This paper was presented at the 24th International Symposium on High-Performance Computer Architecture (HPCA) last month.
-
ReFlex in the news [March 2018]
ReFlex, our software system that provides fast access to remote Flash with quality of service guarantees for latency and throughput, was featured in ZDNet news after winning the NVMW Memorable Paper Award.
-
ML-based prefetching in the news [March 2018]
Our work with Google on ML-based prefetching was summarized in the MIT Technology Review.
-
ReFlex receives Memorable Paper Award [March 2018]
Our work on ReFlex, a system for fast access to remote Flash devices, received a Memorable Paper Award at the 2018 Workshop on Non Volatile Memories. Congrats Ana and Heiner.
-
TETRIS in the news [March 2017]
TETRIS, our scalable and efficient Neural Network accelerator design using 3D DRAM stacks, was covered in the news by The Next Platform. The paper will be presented in the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) in Xi'an, China, in April 2017.
-
ReFlex in the news [March 2017]
ReFlex, our software systems that provides fast access to remote Flash with guaranteed latency and throughput SLOS, was covered in an article by Next Platform.
-
DRAF selected in IEEE Micro Top Picks [February 2017]
Mingyu Gao et al.'s paper "DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric" in ISCA 2016 has been selected in the Special Issue of IEEE Micro: Micro's Top Picks from the 2016 Computer Architecture Conferences, May/June 2017 issue.
-
Three papers receive a 2016 HiPEAC Paper Award [June 2016]
Our papers papers "Generating Configurable Hardware from Parallel Patterns" (ASPLOS'16), "HCloud: Resource-Efficient Provisioning in Shared Cloud Systems" (ASPLOS'16) and "HRL: Efficient and flexible reconfigurable logic for near-data processing" (HPCA'16) received a 2016 HiPEAC paper award.
-
DRAF and DHDL presented at ISCA 2016 [June 2016]
We presented two papers at the 43rd International Symposium on Computer Architecture (ISCA), held in Seoul, South Korea on June 18-22, 2016. Mingyu Gao described "DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric", while David Koeplinger discussed "Automatic Generation of Efficient Accelerators for Reconfigurable Hardware".
- 1 of 6
- ››