Publications
Filters: First Letter Of Last Name is N [Clear All Filters]
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)
"DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Download: paper (1.02 MB); slides (876.98 KB)
"Making nested parallel transactions practical using lightweight hardware support.",
ICS: ACM, pp. 61-71, 2010.
Download: paper (985.03 KB)
"Towards Energy-proportional Datacenter Memory with Mobile DRAM",
Proceedings of the 39th Annual International Symposium on Computer Architecture, Washington, DC, USA, IEEE Computer Society, pp. 37–48, 2012.
Download: paper (5.08 MB)
"DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric",
IEEE Micro Special Issue on Top Picks from the Computer Architecture Conferences, vol. 37, issue 3, 06/2017.
Download: paper (418.24 KB)