Publications
Filters: Author is Olukotun, Kunle [Clear All Filters]
"Plasticine: A Reconfigurable Architecture For Parallel Patterns",
ISCA '17: 44th International Symposium on Computer Architecture, Toronto, Canada, 06/2017.
Abstract
Download: paper (1.53 MB)
"Automatic Generation of Efficient Accelerators for Reconfigurable Hardware",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Abstract
Download: paper (2.77 MB)
"Generating Configurable Hardware from Parallel Patterns",
Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, 04/2016.
Abstract
Download: paper (582.67 KB)
"A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.",
CODES+ISSS: ACM, pp. 513-520, 2012.
Download: paper (402.69 KB)
"Hardware acceleration of transactional memory on commodity systems.",
ASPLOS: ACM, pp. 27-38, 2011.
Download: paper (1.22 MB)
"EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics",
IEEE Intl. Symposium on Workload Characterization (IISWC), Atlanta, GA, 12/2010.
Download: paper (914.55 KB)
"FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.",
FCCM: IEEE Computer Society, pp. 221-228, 2010.
Download: paper (1.05 MB)
"Implementing and Evaluating a Model Checker for Transactional Memory Systems.",
ICECCS: IEEE Computer Society, pp. 117-126, 2010.
Download: paper (286.35 KB)
"Implementing and evaluating nested parallel transactions in software transactional memory.",
SPAA: ACM, pp. 253-262, 2010.
Download: paper (449.46 KB)
"Making nested parallel transactions practical using lightweight hardware support.",
ICS: ACM, pp. 61-71, 2010.
Download: paper (985.03 KB)
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)
"Transactional Memory Coherence and Consistency",
Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, pp. 102–, 6/2004.