Publications

Filters: Author is Kozyrakis, Christos  [Clear All Filters]
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Kozyrakis, C., and D. Patterson, "Overcoming the limitations of conventional vector processors", Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), San Diego, CA, pp. 399–409, 06/2003.
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Labonte, F., P. Mattson, W. Thies, I. Buck, C. Kozyrakis, and M. Horowitz, "The Stream Virtual Machine", Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 267–277, 9/2004.
Leverich, J., and C. Kozyrakis, "Reconciling High Server Utilization and Sub-millisecond Quality-of-Service", Proceedings of the 2014 EuroSys Conference, Amsterdam, Netherlands, 04/2014.
Lo, D., and C. Kozyrakis, "Dynamic Management of TurboMode in Modern Multi-core Chips", 20th Intl. Symposium on High Performance Computer Architecture (HPCA), Orlando, FL, 02/2014.  Download: paper (738.87 KB); slides (1.71 MB)
Lo, D., L. Cheng, R. Govindaraju, L. A. Barroso, and C. Kozyrakis, "Towards Energy Proportionality for Large-Scale Latency-Critical Workloads", International Symposium on Computer Architecture, Minneapolis, Minnesota, 06/2014.  Download: Paper (897.16 KB); Slides (6.82 MB)
Lo, D., L. Cheng, R. Govindaraju, P. Ranganathan, and C. Kozyrakis, "Heracles: Improving Resource Efficiency at Scale", International Symposium on Computer Architecture, Portland, Oregon, 06/2015.  Download: Paper (792.18 KB)
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Malladi, K. T., B. C. Lee, F. A. Nothaft, C. Kozyrakis, K. Periyathambi, and M. Horowitz, "Towards Energy-proportional Datacenter Memory with Mobile DRAM", Proceedings of the 39th Annual International Symposium on Computer Architecture, Washington, DC, USA, IEEE Computer Society, pp. 37–48, 2012.  Download: paper (5.08 MB)
Michelogiannakis, G., D. Sanchez, W. J. Dally, and C. Kozyrakis, "Evaluating Bufferless Flow Control for On-Chip Networks", Proceedings of the 4th ACM/IEEE international symposium on Networks-on-Chip (NOCS-2010), 05/2010.  Download: paper (158.51 KB); slides (897.85 KB)
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Njoroge, N., J. Casper, S. Wee, Y. Teslyar, D. Ge, C. Kozyrakis, and K. Olukotun, "ATLAS: a chip-multiprocessor with transactional memory support", Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.  Download: atlas_date_07.pdf (736.86 KB)
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Oguntebi, T., S. Hong, J. Casper, N. G. Bronson, C. Kozyrakis, and K. Olukotun, "FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.", FCCM: IEEE Computer Society, pp. 221-228, 2010.  Download: paper (1.05 MB)
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Prabhakar, R., Y. Zhang, D. Koeplinger, M. Feldman, T. Zhao, S. Hadjis, A. Pedram, C. Kozyrakis, and K. Olukotun, "Plasticine: A Reconfigurable Architecture For Parallel Patterns", ISCA '17: 44th International Symposium on Computer Architecture, Toronto, Canada, 06/2017. Abstract  Download: paper (1.53 MB)
Prabhakar, R., D. Koeplinger, K. J. Brown, H. J. Lee, C. D. Sa, C. Kozyrakis, and K. Olukotun, "Generating Configurable Hardware from Parallel Patterns", Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, 04/2016. Abstract  Download: paper (582.67 KB)
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Qadeer, W., R. Hameed, O. Shacham, P. Venkatesan, C. Kozyrakis, and M. A. Horowitz, "Convolution Engine: Balancing Efficiency &\#38; Flexibility in Specialized Computing", Proceedings of the 40th Annual International Symposium on Computer Architecture, New York, NY, USA, ACM, pp. 24–35, 2013.  Download: paper (4.78 MB)
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Sanchez, D., and C. Kozyrakis, "The ZCache: Decoupling Ways and Associativity", Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'43), Atlanta, GE, 12/2010.  Download: paper (276.4 KB); slides (752.04 KB)
Sanchez, D., G. Michelogiannakis, and C. Kozyrakis, "An Analysis of Interconnection Networks for Large Scale Chip-Multiprocessors", ACM Transactions on Architecture and Code Optimization (TACO), vol. 7, no. 1, 04/2010.  Download: paper (1.7 MB)
Sanchez, D., and C. Kozyrakis, "Scalable and Efficient Fine-Grained Cache Partitioning with Vantage", IEEE Micro's Top Picks from the Computer Architecture Conferences, vol. 32, no. 3, May-June, 2012.  Download: paper (1.05 MB)
Sanchez, D., and C. Kozyrakis, "SCD: A Scalable Coherence Directory with Flexible Sharer Set Encoding", Proceedings of the 18th international symposium on High Performance Computer Architecture (HPCA-18), New Orleans, LA, 02/2012.  Download: paper (424.5 KB); slides (418.71 KB)
Sanchez, D., D. Lo, R. Yoo, J. Sugerman, and C. Kozyrakis, "Dynamic Fine-Grain Scheduling of Pipeline Parallelism", Proceedings of the 20th Intl. Conference on Parallel Architecture and Compilation Techniques (PACT), Galveston Island, TX, 10/2011.  Download: PDF (336.92 KB)
Sanchez, D., and C. Kozyrakis, "ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems", Proceedings of the 40th annual International Symposium in Computer Architecture (ISCA-40), Tel-Aviv, Israel, 06/2013.  Download: paper (454.61 KB)
Sanchez, D., and C. Kozyrakis, "Vantage: Scalable and Efficient Fine-Grain Cache Partitioning", International Symposium on Computer Architecture (ISCA), San Jose, CA, 06/2011.  Download: paper (753.6 KB); slides (1.74 MB)
Sanchez, D., R. M. Yoo, and C. Kozyrakis, "Flexible Architectural Support for Fine-Grain Scheduling", Proceedings of the 15th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV), 03/2010.  Download: paper (433.69 KB); slides (354.52 KB)
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Talbot, J., R. M. Yoo, and C. Kozyrakis, "Phoenix++: Modular MapReduce for Shared-memory Systems", Proceedings of the Second International Workshop on MapReduce and Its Applications, New York, NY, USA, ACM, pp. 9–16, 2011.  Download: paper (756.45 KB)
Tanaka, S., and C. Kozyrakis, "High Performance Hardware-Accelerated Flash Key-Value Store", the 2014 Non-volatile Memories Workshop (NVMW), San Diego, CA, 03/2014.
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Yoo, R. M., C. J. Hughes, C. Kim, Y. - K. Chen, and C. Kozyrakis, "Locality-aware Task Management for Unstructured Parallelism: A Quantitative Limit Study", Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, New York, NY, USA, ACM, pp. 315–325, 2013.  Download: paper (1.52 MB)
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Zmily, A., and C. Kozyrakis, "Block-aware instruction set architecture", ACM Trans. Archit. Code Optim., vol. 3, no. 3, New York, NY, USA, ACM, pp. 327–357, 2006.  Download: p327-zmily.pdf (526.99 KB)