Publications
"Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks",
Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO), Istanbul, Turkey, pp. 283–293, 11/2002.
"Overcoming the limitations of conventional vector processors",
Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), San Diego, CA, pp. 399–409, 06/2003.
"Scalable Vector Processors for Embedded Systems",
IEEE Micro, vol. 23, no. 6, pp. 36–45, 11/2003.
"Transactional Memory Coherence and Consistency",
Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, pp. 102–, 6/2004.
"The Stream Virtual Machine",
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 267–277, 9/2004.
"Block-aware instruction set architecture",
ACM Trans. Archit. Code Optim., vol. 3, no. 3, New York, NY, USA, ACM, pp. 327–357, 2006.
Download: p327-zmily.pdf (526.99 KB)
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)
"Pointless Tainting?: Evaluating the Practicality of Pointer Tainting",
Proceedings of the 4th ACM European Conference on Computer Systems, New York, NY, USA, ACM, pp. 61–74, 2009.
Download: paper (339.12 KB)
"FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.",
FCCM: IEEE Computer Society, pp. 221-228, 2010.
Download: paper (1.05 MB)
"Implementing and Evaluating a Model Checker for Transactional Memory Systems.",
ICECCS: IEEE Computer Society, pp. 117-126, 2010.
Download: paper (286.35 KB)
"Implementing and evaluating nested parallel transactions in software transactional memory.",
SPAA: ACM, pp. 253-262, 2010.
Download: paper (449.46 KB)
"Making nested parallel transactions practical using lightweight hardware support.",
ICS: ACM, pp. 61-71, 2010.
Download: paper (985.03 KB)
"Server Engineering Insights for Large-Scale Online Services",
IEEE Micro, vol. 30, no. 4, Los Alamitos, CA, USA, IEEE Computer Society Press, pp. 8–19, 2010.
Download: paper (496.53 KB)
"Understanding Sources of Inefficiency in General-purpose Chips",
Proceedings of the 37th Annual International Symposium on Computer Architecture, New York, NY, USA, ACM, pp. 37–47, 2010.
Download: paper (455.9 KB)
"Flexible Architectural Support for Fine-Grain Scheduling",
Proceedings of the 15th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV), 03/2010.
Download: paper (433.69 KB); slides (354.52 KB)
"An Analysis of Interconnection Networks for Large Scale Chip-Multiprocessors",
ACM Transactions on Architecture and Code Optimization (TACO), vol. 7, no. 1, 04/2010.
Download: paper (1.7 MB)
"Evaluating Bufferless Flow Control for On-Chip Networks",
Proceedings of the 4th ACM/IEEE international symposium on Networks-on-Chip (NOCS-2010), 05/2010.
Download: paper (158.51 KB); slides (897.85 KB)
"EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics",
IEEE Intl. Symposium on Workload Characterization (IISWC), Atlanta, GA, 12/2010.
Download: paper (914.55 KB)
"The ZCache: Decoupling Ways and Associativity",
Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'43), Atlanta, GE, 12/2010.
Download: paper (276.4 KB); slides (752.04 KB)
"Hardware acceleration of transactional memory on commodity systems.",
ASPLOS: ACM, pp. 27-38, 2011.
Download: paper (1.22 MB)
"Phoenix++: Modular MapReduce for Shared-memory Systems",
Proceedings of the Second International Workshop on MapReduce and Its Applications, New York, NY, USA, ACM, pp. 9–16, 2011.
Download: paper (756.45 KB)
"Understanding Sources of Ineffciency in General-purpose Chips",
Commun. ACM, vol. 54, no. 10, New York, NY, USA, ACM, pp. 85–93, 2011.
Download: paper (2.83 MB)
"Accurate Modeling and Generation of Storage I/O for Datacenter Workloads",
Exascale Evaluation and Research Techniques Workshop (EXERT), in conjunction with ASPLOS, Newport Beach, CA, 03/2011.
Download: paper (715.38 KB); slides (2.09 MB)
"Storage I/O Generation and Replay for Datacenter Applications",
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, 04/2011.
Download: paper (260.56 KB)
"Vantage: Scalable and Efficient Fine-Grain Cache Partitioning",
International Symposium on Computer Architecture (ISCA), San Jose, CA, 06/2011.
Download: paper (753.6 KB); slides (1.74 MB)