Publications
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"DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric",
IEEE Micro Special Issue on Top Picks from the Computer Architecture Conferences, vol. 37, issue 3, 06/2017.
Download: paper (418.24 KB)
"DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Download: paper (1.02 MB); slides (876.98 KB)
"Generating Configurable Hardware from Parallel Patterns",
Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, 04/2016.
Abstract
Download: paper (582.67 KB)
"The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane",
ACM Trans. Comput. Syst., vol. 34, no. 4, New York, NY, USA, ACM, pp. 11:1–11:39, 2016.
Download: 2016.ix_.tocs_.pdf (1.18 MB)
"The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane",
ACM Trans. Comput. Syst., vol. 34, no. 4, New York, NY, USA, ACM, pp. 11:1–11:39, 2016.
"Towards Energy Proportionality for Large-Scale Latency-Critical Workloads",
International Symposium on Computer Architecture, Minneapolis, Minnesota, 06/2014.
Download: Paper (897.16 KB); Slides (6.82 MB)
"IX: A Protected Dataplane Operating System for High Throughput and Low Latency",
Proceedings of the 11th USENIX Conference on Operating Systems Design and Implementation, Broomfield, CO, USA, USENIX Association, pp. 49–65, 2014.
Download: paper (309.07 KB)
"QoS-Aware Admission Control in Heterogeneous Datacenters",
International Conference on Automated Computing (ICAC), San Jose, CA, 06/2013.
Download: paper (518.36 KB); slides (1.65 MB)
ARQ: A Multi-Class Admission Control Protocol for Heterogeneous Datacenters,
, Stanford, Stanford University, 01/2013.
Download: tech report (663.54 KB)
"Enhanced Concurrency Control with Transactional NACKs,",
8th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Houston, TX, 03/2013, 2012.
Download: paper (203 KB)
"A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.",
CODES+ISSS: ACM, pp. 513-520, 2012.
Download: paper (402.69 KB)
"Dune: Safe User-level Access to Privileged CPU Features",
Proceedings of the 10th USENIX Conference on Operating Systems Design and Implementation, Berkeley, CA, USA, USENIX Association, pp. 335–348, 2012.
Download: paper (251.6 KB)
"Hardware acceleration of transactional memory on commodity systems.",
ASPLOS: ACM, pp. 27-38, 2011.
Download: paper (1.22 MB)
"EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics",
IEEE Intl. Symposium on Workload Characterization (IISWC), Atlanta, GA, 12/2010.
Download: paper (914.55 KB)
"FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.",
FCCM: IEEE Computer Society, pp. 221-228, 2010.
Download: paper (1.05 MB)
"Implementing and Evaluating a Model Checker for Transactional Memory Systems.",
ICECCS: IEEE Computer Society, pp. 117-126, 2010.
Download: paper (286.35 KB)
"Implementing and evaluating nested parallel transactions in software transactional memory.",
SPAA: ACM, pp. 253-262, 2010.
Download: paper (449.46 KB)
"Making nested parallel transactions practical using lightweight hardware support.",
ICS: ACM, pp. 61-71, 2010.
Download: paper (985.03 KB)
"Pointless Tainting?: Evaluating the Practicality of Pointer Tainting",
Proceedings of the 4th ACM European Conference on Computer Systems, New York, NY, USA, ACM, pp. 61–74, 2009.
Download: paper (339.12 KB)
"The Stream Virtual Machine",
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 267–277, 9/2004.