Publications
Filters: First Letter Of Last Name is K [Clear All Filters]
"Hardware acceleration of transactional memory on commodity systems.",
ASPLOS: ACM, pp. 27-38, 2011.
Download: paper (1.22 MB)
"Green enterprise computing data: Assumptions and realities.",
IGCC: IEEE Computer Society, pp. 1-10, 2012.
Download: paper (331.4 KB)
"Generating Configurable Hardware from Parallel Patterns",
Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, 04/2016.
Abstract
Download: paper (582.67 KB)
"Flexible Architectural Support for Fine-Grain Scheduling",
Proceedings of the 15th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV), 03/2010.
Download: paper (433.69 KB); slides (354.52 KB)
"Flash Storage Disaggregation",
Proceedings of the Eleventh European Conference on Computer Systems, London, UK, ACM, pp. 29:1–29:15, 2016.
Download: paper (1.52 MB)
"FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.",
FCCM: IEEE Computer Society, pp. 221-228, 2010.
Download: paper (1.05 MB)
"Evaluating Bufferless Flow Control for On-Chip Networks",
Proceedings of the 4th ACM/IEEE international symposium on Networks-on-Chip (NOCS-2010), 05/2010.
Download: paper (158.51 KB); slides (897.85 KB)
"Enhanced Concurrency Control with Transactional NACKs,",
8th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Houston, TX, 03/2013, 2012.
Download: paper (203 KB)
"EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics",
IEEE Intl. Symposium on Workload Characterization (IISWC), Atlanta, GA, 12/2010.
Download: paper (914.55 KB)
"ECHO: Recreating Network Traffic Maps for Datacenters of Tens of Thousands of Servers",
IEEE International Symposium on Workload Characterization (IISWC), San Diego, CA, 11/2012.
Download: paper (8.76 MB); slides (4.22 MB)
"Dynamic Management of TurboMode in Modern Multi-core Chips",
20th Intl. Symposium on High Performance Computer Architecture (HPCA), Orlando, FL, 02/2014.
Download: paper (738.87 KB); slides (1.71 MB)
"Dynamic Fine-Grain Scheduling of Pipeline Parallelism",
Proceedings of the 20th Intl. Conference on Parallel Architecture and Compilation Techniques (PACT), Galveston Island, TX, 10/2011.
Download: PDF (336.92 KB)
"Dune: Safe User-level Access to Privileged CPU Features",
Proceedings of the 10th USENIX Conference on Operating Systems Design and Implementation, Berkeley, CA, USA, USENIX Association, pp. 335–348, 2012.
Download: paper (251.6 KB)
"DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Download: paper (1.02 MB); slides (876.98 KB)
"DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric",
IEEE Micro Special Issue on Top Picks from the Computer Architecture Conferences, vol. 37, issue 3, 06/2017.
Download: paper (418.24 KB)
"Decoupling Datacenter Studies from Access to Large-Scale Applications: A Modeling Approach for Storage Workloads",
IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, 11/2011.
Download: paper (3.25 MB); slides (2.07 MB)
"Decoupling Datacenter Storage Studies from Access to Large-Scale Applications",
Computer Architecture Letters, vol. 11, issue 2, 2012.
Download: paper (947.88 KB)
"Convolution Engine: Balancing Efficiency &\#38; Flexibility in Specialized Computing",
Proceedings of the 40th Annual International Symposium on Computer Architecture, New York, NY, USA, ACM, pp. 24–35, 2013.
Download: paper (4.78 MB)
"A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.",
CODES+ISSS: ACM, pp. 513-520, 2012.
Download: paper (402.69 KB)
Bolt: Uncovering and Reducing the Security Vulnerabilities of Shared Clouds,
: Cornell University & Stanford University, 04/2016.
Download: paper (2.1 MB)
"Bolt: I Know What You Did Last Summer... In The Cloud",
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, New York, NY, USA, ACM, pp. 599–613, 2017.
"Block-aware instruction set architecture",
ACM Trans. Archit. Code Optim., vol. 3, no. 3, New York, NY, USA, ACM, pp. 327–357, 2006.
Download: p327-zmily.pdf (526.99 KB)
"Automatic Generation of Efficient Accelerators for Reconfigurable Hardware",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Abstract
Download: paper (2.77 MB)
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)
ARQ: A Multi-Class Admission Control Protocol for Heterogeneous Datacenters,
, Stanford, Stanford University, 01/2013.
Download: tech report (663.54 KB)